Cypress Semiconductor /psoc63 /CPUSS /CM0_INT_CTL6

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Interpret as CM0_INT_CTL6

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0MUX0_SEL0MUX1_SEL0MUX2_SEL0MUX3_SEL

Description

CM0+ interrupt control 6

Fields

MUX0_SEL

System interrupt select for CPU interrupt source 24.

MUX1_SEL

System interrupt select for CPU interrupt source 25.

MUX2_SEL

System interrupt select for CPU interrupt source 26.

MUX3_SEL

System interrupt select for CPU interrupt source 27.

Links

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